1. Field of the Invention
The present invention relates generally to the fabrication of substrates including, without limitation, interposers. Specifically, the present invention relates to carrier substrates for use in wafer-level packaging and methods for fabricating conductive elements on surfaces, including via walls, of the substrates.
2. State of the Art
Consumers constantly demand more powerful and smaller electronic products. To produce these products at a reasonable cost to the consumer, the semiconductor industry must continually develop newer and more efficient methods and materials for use in fabricating the electronic products.
Along with the trend in the semiconductor industry to decrease semiconductor device size and increase the density of structures on semiconductor devices, the size of the packages of the modem high-performance and high-functionality integrated circuits (ICs) is also ever-decreasing. Thus, the semiconductor industry has been able to save real estate, or space, and decrease the size of the electronic products by improving the methods and materials used in the packaging process. Along with the space savings, the semiconductor industry has also been able to reduce costs and subsequently pass these savings on to the consumer.
In conventional semiconductor device fabrication processes, a number of discrete semiconductor devices, also termed “dice” or “chips,” such as memory or microprocessor devices, are fabricated on a bulk semiconductor substrate such as a silicon wafer. After the desired structures, circuitry, and other features of each of the semiconductor devices have been fabricated upon the semiconductor substrate, the individual semiconductor devices may be severed or “singulated” from the substrate and packaged. As discussed above, the size of the packages used to package integrated circuits (ICs) has continued to decrease following the trend in the semiconductor industry toward smaller semiconductor components of increased integrated circuit density. One type of semiconductor device package, the so-called “chip-scale package” or “chip-sized package” (“CSP”), consumes about the same amount of real estate upon higher-level packaging, such as a circuit board, as the bare semiconductor device itself. Such chip-scale packages may themselves include a discrete carrier substrate, or interposer, having roughly the same or slightly larger surface area than the bare semiconductor device. Chip-scale packages may also include protective dielectric material, such as a polymer coating or a molded silicon-filled polymer encapsulant, on one or more surfaces of the semiconductor device.
One example of a chip-scale package is a ball grid array package, which may include a semiconductor die disposed on and electrically connected to an interposer. The interposer includes contact pads on a surface thereof opposite that to which the semiconductor die is secured. Electrical traces of the interposer connected to the bond pads of the semiconductor die lead to the contact pads, which are arranged in a different pattern than that of the bond pads of the semiconductor die, thus rerouting or redistributing the connection pattern of the bond pads of the semiconductor die. The contact pads are arranged in a pattern complementary to that of terminals on a higher-level substrate, such as a circuit board, to which the ball grid array package is to be connected and may have discrete conductive elements such as solder balls or conductive or conductor-filled epoxy bumps, studs, columns or pillars formed thereon for effecting the connection.
Recently, there has been an increased interest in fabricating, packaging, and testing semiconductor devices at the so-called wafer level, in which the fabrication, test, and packaging processes are all implemented substantially on a semiconductor wafer or another bulk semiconductor substrate, such as a partial wafer or a so-called “silicon-on-insulator” (SOI) substrate, such as a silicon-on-glass (SOG) substrate, a silicon-on-ceramic (SOC) substrate or a silicon-on-sapphire (SOS) substrate. A package fabricated at the wafer level typically includes a semiconductor substrate provided with a plurality of various conductive elements, such as semiconductor devices with bond pads, external connection elements (e.g., solder balls), redistribution traces connecting the bond pads and the external connection elements, and an insulating material (e.g., a polymer) extending at least over the active surface and sometimes other surfaces of the semiconductor devices. In some instances, an interposer is used to provide redistribution of the bond pad contact pattern of the semiconductor die.
Interposers used in wafer-level-fabricated semiconductor device packages having ball grid array (BGA) connection patterns are manufactured with various conductive layers, insulative layers, and bonding areas used for the subsequent connection of integrated circuits formed on semiconductor dice of the wafer thereto and placement of discrete conductive elements thereon. Vias may also be formed in the interposer substrate to provide connections between various conductive layers of the interposer or through the entire interposer. Metallization techniques using organometallic compounds, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), also known as sputtering, may be used to form conductive layers, from which conductive traces, conductive vias, and other conductive structures may be subsequently patterned, such as by masking and etching processes. The use of such conventional processes to form conductive layers and conductive structures is somewhat undesirable when the conductive structures are to be formed on both major surfaces of a substrate since the substrate must be inverted in order to adequately coat both major surfaces with conductive material. Such conventional processes are also undesirable because the process parameters must be carefully controlled to introduce conductive material into vias or recesses of the substrate without the formation of voids, and such processes are costly and time consuming.
Accordingly, there is a need for methods for more efficiently forming conductive elements on substrates that may be suitable, by way of example only, for use as interposers for wafer-level package fabrication.